A Novel 8T SRAM Cell with Improved Read and Write Margins

被引：0

作者：

Li, Song ^{[1
]}

Lin, Zhiting ^{[1
]}

Zhang, Jiubai ^{[1
]}

Peng, Yuchun ^{[1
]}

Wu, Xiulong ^{[1
]}

机构：

[1] Anhui Univ, Sch Elect & Informat Engn, Hefei 230039, Peoples R China

来源：

PROCEEDINGS OF THE 2015 INTERNATIONAL CONFERENCE ON APPLIED SCIENCE AND ENGINEERING INNOVATION | 2015年 / 12卷

关键词：

Single-bit; SRAM; Stability; RSNM; HSNM; WM;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A highly stable 8T SRAM cell is presented to improve the Static Noise Margin (SNM). The proposed 8T SRAM cell uses a single-bit line structure to perform read and write operation. The design enhances the write ability by breaking-up the feedback loop of the inverter pair. It also improves the read stability by eliminating the effects from the bit-line. The simulations show that the proposed 8T cell offers 2.07x read static noise margin, 1.41x and 2.60x in write '0' margin compared to the conventional 6T cell and 7T cell, respectively. Besides, the proposed structure has a significant improvement in writing '1' operation and HSNM.

引用

页码：679 / 682

页数：4

共 50 条

[1] Improved Read and Write Margins Using a Novel 8T-SRAM Cell
Moradi, Farshad
Madsen, Jens K.
[J]. 2014 22ND INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2014,
[2] A novel 8T SRAM cell with improved read-SNM
Sil, Abhijit
Ghosh, Soumik
Bayoumi, Magdy
[J]. 2007 IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS, 2007, : 253 - 256
[3] A novel 8T SRAM with improved cell density
Reddy, B. Naresh Kumar
Ramalingaswamy, Ch.
Nagulapalli, R.
Ramesh, Dharavath
[J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2019, 98 (02) : 357 - 366
[4] A novel 8T SRAM with improved cell density
B. Naresh Kumar Reddy
Ch. Ramalingaswamy
R. Nagulapalli
Dharavath Ramesh
[J]. Analog Integrated Circuits and Signal Processing, 2019, 98 : 357 - 366
[5] 8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology
Moradi, Farshad
Tohidi, Mohammad
Zeinali, Behzad
Madsen, Jens K.
[J]. VLSI-SOC: INTERNET OF THINGS FOUNDATIONS, 2015, 464 : 95 - 109
[6] A Novel Single Ended 8T SRAM with Improved Noise Margins and Stability
Narayan, Jay
Sharma, R. K.
[J]. 2014 RECENT ADVANCES IN ENGINEERING AND COMPUTATIONAL SCIENCES (RAECS), 2014,
[7] An 8T SRAM Cell with Improved ION/IOFF Ratio and with Faster Read Speed
Goswami, Abhinandan
Rajput, Amit Singh
Sxena, Nikhil
[J]. JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES, 2020, 15 (1-2): : 127 - 136
[8] A Novel Power Efficient 8T SRAM Cell
Sindwani, Ankush
Saini, Suman
[J]. 2014 RECENT ADVANCES IN ENGINEERING AND COMPUTATIONAL SCIENCES (RAECS), 2014,
[9] An 8T TG-DTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times
Chunn, Ankush
Agrawal, Akshay
Naugarhiya, Alok
[J]. 2020 24TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2020,
[10] Novel Asymmetric 8T SRAM Cell with Dynamic Power
Mo, Yi-Nan
Hang, Guo-Qiang
Zhang, Dan-Yan
[J]. 2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 1480 - 1482

← 1 2 3 4 5 →