Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks

Spin-transfer-torque magnetoresistive random-access memory (STT-MRAM) is a promising candidate for future memory systems, however, implementing highly parallel neuro-inspired computing with standard STT-MRAM arrays faces the power consumption challenges due to the low resistance characteristics of the magnetic tunneling junction (MTJ). In this brief, we propose a novel in-memory computing (IMC) architecture for binary neural network (BNN). The proposed design is constructed with short-circuit-logic-based 3-transistor and 2-MTJ (3T2J-S) bit-cell to implement XNOR operations and series-connected crossbar array for bit-counting operations. By further sharing the active region, the layout area of the proposed 3T2J-S bit-cell is reduced by 20% compared with the conventional STT-MRAM crossbar bit-cell. Moreover, the proposed design can optimize the write asymmetry issue of STT-MRAM, thereby reducing the voltage required for the write operation. Furthermore, the proposed 3T2J-S bit-cell has the same on/off ratio as the conventional one, and can increase the inference frequency by 10.6% due to the reduction of the bit-cell resistance.