Energy and Area Efficient Tunnel FET-based Spiking Neural Networks

Exploiting the Tunnel FET (TILT) properties such as unidirectional conduction and asymmetric drain and source, we propose for the first time a novel TFET-based circuit design mechanism for spike timing dependent plasticity process. In the proposed circuit, we are able to reduce the transistor count by half, making the circuit more area and energy efficient. A neuron receiving input from ten synapses, containing the proposed learning circuit, was simulated and it operated with reduced area and energy consumption compared to the MOSFET-based implementation.