An energy and area-efficient spike frequency adaptable LIF neuron for spiking neural networks

As Moore's law approaches its limit, conventional computing methods face energy efficiency challenges, prompting the exploration of alternative information processing methods like spiking neural networks (SNNs). Neurons, the fundamental unit of the nervous system, are crucial for efficiently implementing SNNs in hardware, requiring energy and area-efficient design. This paper presents novel circuit designs for the leaky integrate-and-fire (LIF) neuron model at 7 nm FinFET technology, including 8T FinFET LIF Neuron 1, 7T FinFET LIF Neuron 2, 7T FinFET LIF Neuron 3 and 6T FinFET LIF Neuron 4. In the proposed configurations of LIF neuron, the energy per spike is reduced by 95.80 %, 95.89 %, 95.89 %, 96.76 %, and 96.65 % in the 8T FinFET LIF neuron 1 (case 1), 8T FinFET LIF neuron 1 (case 2), 7T FinFET LIF Neuron 2, 7T FinFET LIF Neuron 3, and 6T FinFET LIF Neuron 4, respectively, compared to the lowest energy per spike reported in the literature, with the minimum known energy per spike being 0.67 fJ. The proposed FinFET neurons offer attractive hardware acceleration (spiking frequency in the MHz range), minimal energy per spike (fJ range), simplicity, and area efficiency, making them more biologically plausible due to their adaptable spiking frequency.