A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and selflocking comparators

This paper presents a 6-b successive approximation register(SAR) ADC at the sampling rate of600 MHz in a 65 nm CMOS process.To pursue high speed,this design employs the idea of the 2-b/stage.Based on this,the proposed structure with a new switching procedure is presented.Compared with traditional structures,it optimizes problems cause by mismatches of DACs and saves power.In addition,this paper takes advantage of distributed comparator topology to improve the speed,while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators.The measurement results demonstrate that the signal-tonoise plus distortion ratio(SNDR) is 32.13 dB and the spurious-free dynamic range(SFDR) is 44.05 dB at 600MS/s with 5.6 MHz input.By contrast,the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input.Fabricated in a TSMC 65 nm process,the SAR ADC core occupies an area of 0.045 mm2 and consumes power of5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step.