Automating the sizing of analog CMOS circuits by consideration of structural constraints

被引：10
|
作者：
Schwencker, R [1 ]
Eckmueller, J [1 ]
Graeb, H [1 ]
Antreich, K [1 ]
机构：
[1] Tech Univ Munich, Inst Elect Design Automat, D-80290 Munich, Germany
来源：
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS | 1999年
关键词：
D O I：
10.1109/DATE.1999.761141
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and are introduced as structural constraints into the sizing process. Systematic consideration of these structural constraints during the automatic sizing prevents pathologically sized circuits and speeds up the automatic sizing. The sizing is done with a sensitivity-based, iterative trust region method.
引用
收藏
页码：323 / 327
页数：5
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