Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond

CMOS scaling so far enabled simultaneous system throughput scaling by concurrent improvements in delay, power, and area with thanks to Moore's law. CMOS scaling becomes more difficult with the limits of interconnect and increasing wafer cost. Increasing resistance of the interconnect and increasing device parasitics limit the gains from any device improvement because of voltage drops. In this paper we will address various mitigation approaches in both technology and design to enable PPA (Performance-Power-Area) scaling for the 5 nm technology node and beyond. Technology solutions include low-k device spacers, wrap-around contact for improved device parasitics and non-Cu based interconnects for improved interconnect resistance. Design solutions focus on improving cell drive by optimally sizing the device and focus on key layout constructs for lowering the impact of parasitics while enabling much more compact standard cells. Finally, we point out challenges of increasing power density by scaling and tightening defectivity control, particularly in 3D integration.