Density Aware Cell Library Design for Design-Technology Co-Optimization

This paper proposes a model to estimate the best layout style to maximize its power performance and area. Diffusion jogging is widely used to reduce its gate capacitance however sparse layout sometimes requires more area to improve layer density. Standard cell libraries with various layout styles were designed in commercial 65-nm process and evaluated its energy consumption and area considering its density constraint. Density aware library achieves 19% area reduction at the cost of 1.9% energy overhead.