Design technology co-optimization towards sub-3 nm technology nodes

Over the past half century, Moore's Law has played a crucial role in the development of the semiconductor field, which depends on straightforwardly dimensional scaling with approximately a two-year cadence. Significant benefits of performance, power, area, and cost (PPAC) in microchips are expected at each technology node. However, aggressive pitch-based scaling by resolution enhancement techniques be-comes increasingly challenging to sustain. Short-channel effects, e.g. high leakage current, drain induced barrier lowering effect, deteriorate the device performance greatly. There-fore, the migration of device architecture from planar to 3D fin structures has been adopted to continue the pace of further scaling due to superior electrostatic controllability. Currently, the gate length at 5 nm technology node in 2020 is shrunk incredibly to less than 12 nm, approaching quantum-mechanical limitations. To address the continuous scaling is-sues, a joint design-technology co-optimization (DTCO) effort between process flow and design definition has been already developed, which helps to manage ramping advanced technology nodes by identifying scaling bottlenecks early and finding paths without overburdening either the design or the process points. With this methodology, Moore's Law can continue to fuel its life towards sub-3 nm nodes.