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- [1] Design-Technology Co-Optimization of Anti-Fuse Memory on Intel 22nm FinFET Technology 2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2019,
- [2] Design and Process Co-optimization for 28nm/22nm and Beyond - A Foundry's Perspective 2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 418 - 418
- [3] Technology Roadmap for 22nm and Beyond 2009 2ND INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY, 2009, : 188 - 191
- [5] Design/System Technology Co-Optimization for 3nm Node and Beyond 2021 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), 2021,
- [6] Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue PROCEEDINGS OF THE 2016 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN (ISPD'16), 2016, : 89 - 89
- [7] Creating an Affordable 22nm Node Using Design-Lithography Co-Optimization DAC: 2009 46TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2009, : 95 - 96
- [8] Design-Technology Co-Optimization of Sequential and Monolithic CFET as enabler of technology node beyond 2nm DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION XV, 2021, 11614