DESIGN OF C-TESTABLE DCVS BINARY ARRAY DIVIDERS

Clocked differential cascode voltage switch (DCVS) circuits are dynamic CMOS circuits that have the advantage of being protected against test-set invalidation due to circuit delays and timing skews. In this paper we consider the problem of testing of DCVS binary array dividers. Both the nonrestoring and restoring array dividers are considered. We show that a DCVS nonrestoring array divider can be made C-testable with only either four or five vectors. These vectors detect all the detectable single stuck-at, stuck-open, and stuck-on faults in the circuit. The additional hardware required to achieve C-testability for an n x n nonrestoring array divider only consists of n - 1 two-input XOR gates and one control input. We show that a restoring DCVS binary array divider can be made C-testable with only six vectors, which also detect all the detectable single stuck-at, stuck-open, and stuck-on faults in the circuit. The hardware overhead required for the C-testable design of the n x n restoring array divider consists of n two-input XOR gates and one control input.