共 50 条
- [1] A COMPARISON OF TRENCH FILLING MATERIALS FOR SUB-MICRON CMOS [J]. JOURNAL DE PHYSIQUE, 1988, 49 (C-4): : 537 - 540
- [3] LITHOGRAPHY FOR A SUB-MICRON CMOS PROCESS [J]. PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1985, 538 : 46 - 50
- [4] Library building for sub-micron CMOS process [J]. 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 1369 - 1372
- [7] CHARACTERIZATION OF NARROW-SPACED ISOLATION IN A TWIN RETROGRADE WELL SUB-MICRON CMOS PROCESS [J]. JOURNAL DE PHYSIQUE, 1988, 49 (C-4): : 29 - 32
- [8] Process factors in the reduction of output conductance in sub-micron CMOS [J]. NSTI NANOTECH 2004, VOL 1, TECHNICAL PROCEEDINGS, 2004, : 477 - 480
- [9] Channel engineering for sub-micron CMOS technologies [J]. PROCEEDINGS OF THE ELEVENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOL 1 & 2, 2002, 4746 : 637 - 640
- [10] GATE MATERIALS CONSIDERATION FOR SUB-MICRON CMOS [J]. APPLIED SURFACE SCIENCE, 1989, 38 (1-4) : 416 - 428