Channel engineering for sub-micron CMOS technologies

被引：0

作者：

Dixit, A ^{[1
]}

Pal, DK ^{[1
]}

Roy, JN ^{[1
]}

Rao, VR ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Bombay 076, Maharashtra, India

来源：

PROCEEDINGS OF THE ELEVENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOL 1 & 2 | 2002年 / 4746卷

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, we have applied channel-engineering strategies for the Semiconductor Complex Limited (SCL) 0.8 mum CMOS process and studied the performance advantages using extensive 2-D device simulations. Our results clearly indicate that, with minimum adjustments to the process flow, one can achieve improved performance by appropriate choice of channel engineering techniques.

引用

页码：637 / 640

页数：4

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