A RESIDUE ARITHMETIC IMPLEMENTATION OF THE FFT

被引:2
|
作者
TAYLOR, FJ
机构
[1] Univ of Florida, Gainesville, FL,, USA, Univ of Florida, Gainesville, FL, USA
关键词
D O I
10.1016/0743-7315(87)90004-9
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
MATHEMATICAL TRANSFORMATIONS
引用
收藏
页码:191 / 208
页数:18
相关论文
共 50 条
  • [11] A FAST NEAR OPTIMUM VLSI IMPLEMENTATION OF FFT USING RESIDUE NUMBER-SYSTEMS
    ALIA, G
    BARSI, F
    MARTINELLI, E
    [J]. INTEGRATION-THE VLSI JOURNAL, 1984, 2 (02) : 133 - 147
  • [12] Arithmetic test strategy for FFT processor
    Xiao, JX
    Chen, GJ
    Xie, YL
    [J]. 14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2005, : 440 - 443
  • [13] A SIMPLE FFT BUTTERFLY ARITHMETIC UNIT
    WHITE, SA
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1981, 28 (04): : 352 - 355
  • [14] The Implementation of Two Channel IIR Quadrature Mirror Filter Bank Based on Residue Arithmetic
    Stamenkovic, Negovan
    Zivaljevic, Dragana
    Stojanovic, Vidosav
    Krstic, Ivan
    [J]. 2014 18TH INTERNATIONAL SYMPOSIUM ON ELECTRICAL APPARATUS AND TECHNOLOGIES (SIELA), 2014,
  • [15] Residue arithmetic circuits based on signed-digit number representation and the VHDL implementation
    Wei, SG
    Shimizu, K
    [J]. NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, : 218 - 221
  • [16] Optimizing Residue Arithmetic on FPGAs
    Fu, Haohuan
    Mencer, Oskar
    Luk, Wayne
    [J]. PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, 2008, : 41 - 48
  • [17] Residue arithmetic in FPGA matrices
    Tomczak, Tadeusz
    [J]. DEPCOS-RELCOMEX 2006, 2006, : 297 - 304
  • [18] USE OF RESIDUE ARITHMETIC FOR COMPUTATION
    BANERJI, DK
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1974, C 23 (12) : 1315 - 1317
  • [19] ON IMPLEMENTING THE CRT IN RESIDUE ARITHMETIC
    DIRR, W
    TAYLOR, FJ
    [J]. INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS, 1985, 17 (02) : 155 - 163
  • [20] A VLSI RESIDUE ARITHMETIC MULTIPLIER
    TAYLOR, FJ
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1982, 31 (06) : 540 - 546