Arithmetic test strategy for FFT processor

For Fast Fourier Transform (FFT) processors, this paper presents a novel pseudo-exhaustive test strategy, in which adders in FFT processor generate all the test patterns. The scheme can detect all combinational faults within every basic building cell of FFT processors. Because of the reuse of some building blocks such as adders and registers existing in FFT processor, and the regularity of the circuit structure, the test scheme can be implemented at-speed and in parallel without performance degradation and additional hardware overhead, and with minimal additional area overhead.