Residue arithmetic circuits based on signed-digit number representation and the VHDL implementation

被引：1

作者：

Wei, SG ^{[1
]}

Shimizu, K ^{[1
]}

机构：

[1] Gunma Univ, Dept Comp Sci, Kiryu, Gumma 376, Japan

来源：

NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/GLSV.1999.757414

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Residue arithmetic circuits based on radix-2 signed-digit(SD) number representation, using integers 2(P) and 2(P) +/- 1 as moduli of residue number system(RNS)! are presented. The modulo m addition, m = 2(P) or m 2(P) +/- 1, is performed by a carry-free SD adder and the modulo m multiplier is constructed using a binary module Tn SD adder tree. The implementation for the residue arithmetic circuits with VHDL description is proposed. The modulo m adders and multipliers have about 530 and 5000 gates, respectively, in cases of m = 2(16) +/- 1.

引用

页码：218 / 221

页数：4

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