LOW-LATENCY BIT-PARALLEL SYSTOLIC MULTIPLIER

被引：2
|
作者：
PEKMESTZI, KZ
CARAISCOS, C
机构：
[1] National Technical University of Athens, Department of Electrical Engineering, 157 73 Zographou, Athens
来源：
ELECTRONICS LETTERS | 1993年 / 29卷 / 04期
关键词：
PARALLEL MULTIPLIERS; SYSTOLIC ARRAYS;
D O I：
10.1049/el:19930247
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A bit-parallel systolic multiplier based on pair-wise grouping of the bit products is presented. The proposed scheme yields significantly lower latency compared to existing systolic multipliers, without increasing the circuit complexity. High throughput is achieved, limited by the delay of a gated full adder and a latch.
引用
收藏
页码：367 / 369
页数：3
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