Evaluation of the maximum number of switching gates for CMOS circuits

This paper addresses the problem of evaluating the maximum number of switching gates. We propose both exact and approximate algorithms to evaluate the maximum or nearly maximum number of switching gates based on the branch-and-bound method. In these methods, iterations of partially exhaustive enumeration and information from circuit structure are used to prune the search space. These methods are implemented on Sun workstations and experiments for ISCAS'85 and ISCAS'89 benchmark circuits have been done. For small circuits, the maximum number of switching gates can be easily evaluated using the exact algorithm. For large circuits, results for the approximate algorithm are compared with results obtained by applying randomly generated vector pairs. It has been shown that the approximate method is better than the latter.