LOW OVERHEAD DESIGN FOR PROGRAMMABLE LOGIC ARRAY WITH TESTABILITY

被引：0
|
作者：
WEI, KC
SHEU, JJ
LIU, BD
机构：
[1] Department of Electrical Engineering, National Cheng Kung University, Tainan
来源：
INTERNATIONAL JOURNAL OF ELECTRONICS | 1994年 / 77卷 / 02期
关键词：
D O I：
10.1080/00207219408926053
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new design to reduce the overhead required for a fully testable PLA is proposed. This design rearranges and groups the product lines into partitions. Then, one extra output line per partition is added to make the whole PLA testable. The silicon area overhead required by this design is significantly less than those of previous methods.
引用
收藏
页码：241 / 250
页数：10
相关论文
共 50 条
  • [41] INTEGRATED PROGRAMMABLE LOGIC ARRAY TRIGGERS
    MANUKYAN, EM
    TELECOMMUNICATIONS AND RADIO ENGINEERING, 1989, 44 (12) : 99 - 102
  • [42] INTRODUCTION TO PROGRAMMABLE ARRAY LOGIC.
    Coli, Vincent J.
    Byte, 1987, 12 (0l): : 207 - 2
  • [43] Determination of the delay of a programmable logic array
    Avdeev N.A.
    Bibilo P.N.
    Russian Microelectronics, 2010, 39 (04) : 288 - 298
  • [44] LOGIC DESIGN AND PROGRAMMABLE LOGIC DEVICES
    Petrescu, I
    Pavaloiu, I. B.
    Raducanu, M.
    Marian, V. C.
    Mitrea, D. A.
    Bratosin, I. A.
    Dragoi, G.
    13TH INTERNATIONAL TECHNOLOGY, EDUCATION AND DEVELOPMENT CONFERENCE (INTED2019), 2019, : 9093 - 9097
  • [45] Design of multiple-valued programmable logic array with unary function generators
    Hata, Y
    Kamiura, N
    Yamato, K
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1999, E82D (09) : 1254 - 1260
  • [46] A new design for programmable logic array based on QCA-based nanotechnology
    Ru-Jia Wang
    Yi-Peng Xu
    She, Chen
    Nasution, Mahyuddin
    OPTIK, 2022, 253
  • [47] A PROGRAMMABLE LOGIC ARRAY SUITABLE FOR USE IN DIGITAL SYSTEM-DESIGN LABORATORIES
    ABE, K
    OMORI, T
    NARAOKA, M
    IEEE TRANSACTIONS ON EDUCATION, 1992, 35 (04) : 338 - 350
  • [48] IAPDL-based low-power adiabatic programmable logic array
    Lau, KT
    Liu, F
    MICROELECTRONICS JOURNAL, 2000, 31 (04) : 235 - 238
  • [49] LOGIC DESIGN STRUCTURE FOR LSI TESTABILITY.
    Eichelberger, E.B.
    Williams, T.W.
    1600, (02):
  • [50] DESIGN OF LOGIC NETWORKS WITH REDUNDANCY AND TESTABILITY CONSIDERATIONS
    DANDAPANI, R
    REDDY, SM
    IEEE TRANSACTIONS ON COMPUTERS, 1974, C 23 (11) : 1139 - 1149
12345