Design of multiple-valued programmable logic array with unary function generators

被引:0
|
作者
Hata, Y [1 ]
Kamiura, N
Yamato, K
机构
[1] Himeji Inst Technol, Dept Comp Engn, Himeji, Hyogo 6712201, Japan
[2] Hyogo Univ, Dept Econ & Informat Sci, Kakogawa 6750101, Japan
关键词
multiple-valued logic; programmable logic array; unary function; logic design; minimization;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes the benefit of utilizing the unary function generators in a multiple-valued Programmable Logic Array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM-form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as ([log(2) p]-p upsilon + p(n - upsilon) + 1) p(n-1) to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.
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页码:1254 / 1260
页数:7
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