Minimization algorithms for multiple-valued programmable logic arrays

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作者：

机构：

[1] Tirumalai, Parthasarathy P.

[2] Butler, Jon T.

来源：

Tirumalai, Parthasarathy P. | 1600年 / 40期

关键词：

Computational Complexity - Heuristic Algorithms - Logic Minimization - Programmable Logic Arrays (PLA);

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[1] MINIMIZATION ALGORITHMS FOR MULTIPLE-VALUED PROGRAMMABLE LOGIC-ARRAYS
TIRUMALAI, PP
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[2] A heat quench algorithm for the minimization of multiple-valued programmable logic arrays
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[J]. COMPUTERS & ELECTRICAL ENGINEERING, 1996, 22 (02) : 103 - 107
[3] Multiple-valued logic minimization by genetic algorithms
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[J]. 27TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - 1997 PROCEEDINGS, 1997, : 97 - 102
[4] MULTIPLE-VALUED LOGIC AND OPTIMIZATION OF PROGRAMMABLE LOGIC-ARRAYS
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[5] Multiple-valued programmable logic arrays with universal literals
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[7] Development of Programmable Logic Array for Multiple-Valued Logic Functions
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[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (12) : 4854 - 4866
[8] MULTIPLE-VALUED DECOMPOSITION OF GENERALIZED BOOLEAN FUNCTIONS AND THE COMPLEXITY OF PROGRAMMABLE LOGIC-ARRAYS
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[J]. IEEE TRANSACTIONS ON COMPUTERS, 1981, 30 (09) : 635 - 643
[9] Minimization of multiple-valued logic expressions with Kleenean coefficients
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[J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1996, E79D (03) : 189 - 195
[10] DESIGN OF REPAIRABLE CELLULAR ARRAYS ON MULTIPLE-VALUED LOGIC
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