LOW OVERHEAD DESIGN FOR PROGRAMMABLE LOGIC ARRAY WITH TESTABILITY

被引：0
|
作者：
WEI, KC
SHEU, JJ
LIU, BD
机构：
[1] Department of Electrical Engineering, National Cheng Kung University, Tainan
来源：
INTERNATIONAL JOURNAL OF ELECTRONICS | 1994年 / 77卷 / 02期
关键词：
D O I：
10.1080/00207219408926053
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new design to reduce the overhead required for a fully testable PLA is proposed. This design rearranges and groups the product lines into partitions. Then, one extra output line per partition is added to make the whole PLA testable. The silicon area overhead required by this design is significantly less than those of previous methods.
引用
收藏
页码：241 / 250
页数：10
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