共 50 条
- [1] A new logic transformation method for both low power and high testability PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 2000, : 332 - 335
- [2] A new logic transformation method for both low power and high testability INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2004, 3254 : 770 - 779
- [4] Considering testability during high-level design Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 1998, : 205 - 210
- [6] Clock switching: A new Design for current Testability (DcT) method for dynamic logic circuits 1998 IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, PROCEEDINGS, 1998, : 20 - 25
- [7] Considering testability during high-level design PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98, 1998, : 205 - 210
- [8] Design method of high performance and low power functional units considering delay variations IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2006, E89A (12): : 3519 - 3528
- [9] A New Design-for-Testability Method Based on Thru-Testability JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2011, 27 (05): : 583 - 598
- [10] A New Design-for-Testability Method Based on Thru-Testability Journal of Electronic Testing, 2011, 27 : 583 - 598