A new logic design method for considering low power and high testability

被引:0
|
作者
Son, YS [1 ]
Chong, JW [1 ]
机构
[1] Hanyang Univ, Dept Elect Engn, Seongdong Ku, Seoul 133791, South Korea
关键词
logic transformation; testability; DFT; BIST;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, a new logic transformation method to achieve both low power consumption and high testability is proposed. Our method is based on the redundancy insertion approach. We describe the structure of redundant connections that operate as test points in the test mode. The results of experiments on MCNC benchmark circuits show that the transformed circuit consumes less power in the normal mode and has higher testability in the test mode than the original circuit.
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页码:327 / 338
页数:12
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