A new logic transformation method for both low power and high testability

被引：0

作者：

Son, YS ^{[1
]}

Chong, JW ^{[1
]}

机构：

[1] Hanyang Univ, Dept Elect Engn, Seongdong Ku, Seoul 133791, South Korea

来源：

PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III | 2000年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a new logic transformation method to achieve both low power consumption and high testability is proposed. Our method is based on the redundancy insertion approach. We also describe the structure of redundant connections that operate as test points in the test mode. The results of experiments on MCNC benchmark circuits show that the transformed circuit consumes less power in the normal mode and has higher testability in the test mode than the original circuit.

引用

页码：332 / 335

页数：4

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