EXPERIMENTAL REALIZATION OF A FULL ADDER BY SUBSTRATE FED THRESHOLD LOGIC STRUCTURE

被引：0
|
作者：
HAN, CH
KIM, CK
机构：
来源：
ELECTRONICS LETTERS | 1983年 / 19卷 / 16期
关键词：
D O I：
10.1049/el:19830418
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：613 / 615
页数：3
相关论文
共 50 条
  • [41] IMPROVEMENTS IN CIRCUIT REALIZATION OF THRESHOLD-LOGIC GATES
    HURST, SL
    ELECTRONICS LETTERS, 1973, 9 (06) : 123 - 124
  • [42] REALIZATION OF A BOOLEAN FUNCTION USING AN EXTENDED THRESHOLD LOGIC - 1. REALIZATION OF A 2ND-ORDER THRESHOLD FUNCTION USING AN EXTENDED THRESHOLD LOGIC.
    Oyagi, Shigeo
    Sanechika, Noriaki
    Mori, Ryoichi
    1978, 42 (10): : 757 - 774
  • [43] A full adder implementation using SET based linear threshold gates
    Lageweg, C
    Cotofana, S
    Vassiliadis, S
    ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS, 2002, : 665 - 668
  • [44] Leakage Minimization in Full Adder by Using Sub-Threshold Technique
    Gautam, Surabhi
    Singh, Man Mohan
    Bhadauria, Vijaya
    Siddiqui, M. J.
    PROCEEDINGS OF THE 2017 INTERNATIONAL CONFERENCE ON MULTIMEDIA, SIGNAL PROCESSING AND COMMUNICATION TECHNOLOGIES (IMPACT), 2017, : 142 - 146
  • [45] REALIZATION OF LOGIC FUNCTIONS BY MULTI-OUTPUT THRESHOLD-LOGIC GATES
    BENNETT, LAM
    IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1982, 129 (06): : 239 - 243
  • [46] Performance Analysis of 1 bit Full Adder Using GDI Logic
    Mohan, Shoba
    Rangaswamy, Nakkeeran
    2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
  • [47] Low-power logic styles for full-adder circuits
    Quintana, JM
    Avedillo, MJ
    Jiménez, R
    Rodríguez-Villegas, E
    ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS, 2001, : 1417 - 1420
  • [48] Design and Analysis of Energy Efficient Reversible Logic based Full Adder
    Pujar, Jagadeesh
    Raveendran, Sithara
    Panigrahi, Trilochan
    Vasantha, M. H.
    Kumar, Nithin Y. B.
    2019 IEEE 62ND INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2019, : 339 - 342
  • [49] Compact MEMS modeling to design full adder in Capacitive Adiabatic Logic
    Galisultanov, Ayrat
    Perrin, Yann
    Fanet, Herve
    Hutin, Louis
    Pillonnet, Gael
    2018 48TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2018, : 174 - 177
  • [50] A Low Power Multiplexer Based Pass Transistor Logic Full Adder
    Kamsani, Noor Ain
    Thangasamy, Veeraiyah
    Hashim, Shaiful Jahari
    Bukhori, Muhammad Faiz
    Yusoff, Zubaida
    Hamidon, Mohd Nizar
    2015 IEEE REGIONAL SYMPOSIUM ON MICRO AND NANOELECTRONICS (RSM), 2015, : 176 - 179
12345