SYMMETRIZING A HESSENBERG MATRIX - DESIGNS FOR VLSI PARALLEL PROCESSOR ARRAYS

被引:0
|
作者
KUMAR, FRK [1 ]
SEN, SK [1 ]
机构
[1] INDIAN INST SCI,SUPERCOMP EDUC & RES CTR,BANGALORE 560012,KARNATAKA,INDIA
来源
PROCEEDINGS OF THE INDIAN ACADEMY OF SCIENCES-MATHEMATICAL SCIENCES | 1995年 / 105卷 / 01期
关键词
COMPLEXITY; EQUIVALENT SYMMETRICAL MATRIX; HESSENBERG MATRIX; SYMMETRIZER; SYSTOLIC ARRAY; VLSI PROCESSOR ARRAY;
D O I
10.1007/BF02840591
中图分类号
O1 [数学];
学科分类号
0701 ; 070101 ;
摘要
A symmetrizer of a nonsymmetric matrix A is the symmetric matrix X that satisfies the equation XA = A(t)X, where t indicates the transpose. A symmetrizer is useful in converting a nonsymmetric eigenvalue problem into a symmetric one which is relatively easy to solve and finds applications in stability problems in control theory and in the study of general matrices. Three designs based on VLSI parallel processor arrays are presented to compute a symmetrizer of a lower Hessenberg matrix. Their scope is discussed. The first one is the Leiserson systolic design while the remaining two, viz., the double pipe design and the fitted diagonal design are the derived versions of the first design with improved performance.
引用
收藏
页码:59 / 71
页数:13
相关论文
共 50 条
  • [41] Parallel reconfiguration algorithms for mesh-connected processor arrays
    Jigang Wu
    Guiyuan Jiang
    Yuze Shen
    Siew-Kei Lam
    Jizhou Sun
    Thambipillai Srikanthan
    The Journal of Supercomputing, 2014, 69 : 610 - 628
  • [42] Parallel ART for image reconstruction in CT using processor arrays
    Gordon, Dan
    INTERNATIONAL JOURNAL OF PARALLEL EMERGENT AND DISTRIBUTED SYSTEMS, 2006, 21 (05) : 365 - 380
  • [43] Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access
    Hariyama, M
    Sasaki, H
    Kameyama, M
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2005, E88D (07): : 1486 - 1491
  • [44] DYNAMICALLY RULE-PROGRAMMABLE VLSI PROCESSOR FOR FULLY-PARALLEL INFERENCE
    HANYU, T
    TAKEDA, K
    HIGUCHI, T
    ELECTRONICS LETTERS, 1992, 28 (07) : 695 - 697
  • [45] Reconfigurable parallel VLSI co-processor for space robots using FPGA
    Wei, R.
    Jin, M. H.
    Xia, J. J.
    Xie, Z. W.
    Liu, H.
    2006 IEEE INTERNATIONAL CONFERENCE ON ROBOTICS AND BIOMIMETICS, VOLS 1-3, 2006, : 374 - +
  • [47] Interfacing MATLAB with a parallel virtual processor for matrix algorithms
    Hoffbeck, JP
    Sarwar, M
    Rix, EJ
    JOURNAL OF SYSTEMS AND SOFTWARE, 2001, 56 (01) : 77 - 80
  • [48] PARALLEL MATRIX MULTIPLICATION ON AN ARRAY-LOGICAL PROCESSOR
    VILSER, RJ
    CREUTZBURG, R
    GOSSEL, M
    GRUNDMANN, HJ
    RECENT ISSUES IN PATTERN ANALYSIS AND RECOGNITION, 1989, 399 : 72 - 78
  • [49] PARALLEL MATRIX MULTIPLICATION ON AN ARRAY-LOGICAL PROCESSOR
    VILSER, RJ
    CREUTZBURG, R
    GOSSEL, M
    GRUNDMANN, HJ
    LECTURE NOTES IN COMPUTER SCIENCE, 1989, 399 : 72 - 78
  • [50] Parallel algorithms for reduction of a general matrix to upper Hessenberg form on a shared memory multiprocessor
    Kaya, D
    Wright, K
    APPLIED MATHEMATICS AND COMPUTATION, 2005, 165 (01) : 195 - 212