GRAPE-II - A SYSTEM-LEVEL PROTOTYPING ENVIRONMENT FOR DSP APPLICATIONS

被引:35
|
作者
LAUWEREINS, R
ENGELS, M
ADE, M
PEPERSTRAETE, JA
机构
关键词
D O I
10.1109/2.347998
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Grape-II (Graphical Rapid Prototyping Environment) is an advanced system-level development environment for specifying, compiling, debugging, simulating, and emulating digital-signal-processing applications. Its structured prototyping methodology reduces programming effort, and its use of general-purpose reusable hardware minimizes development cost. The general-purpose hardware consists of commercial DSP processors, bond-out versions of core processors, and FPGAs linked to form a powerful, heterogeneous multiprocessor, such as the Paradigm RP developed within the Retides (Real-Time DSP Emulation System) Esprit project and marketed by InCA/Zycad. Grape-II automates the prototyping methodology for these systems by offering tools for resource estimation, partitioning, assignment, routing, scheduling, code generation, and parameter modification. This prototyping approach has been successfully used for an audio processor for the consumer market, for a sender, receiver and channel simulator for digital audio broadcasting, and for a real-time video encoder for mobile applications. The video-encoder case study, described in the article, resulted in a full-speed operational prototype. This and other successes demonstrate the feasibility of the authors' strategy for prototyping real-time color video compression on a commercial DSP multiprocessor.
引用
收藏
页码:35 / 43
页数:9
相关论文
共 50 条
  • [1] System-level virtual prototyping
    Emery, PJ
    COMPUTER GRAPHICS WORLD, 1999, 22 (05) : 22 - 22
  • [2] System-level modeling of DSP and embedded processors
    Zivojnovic, V
    Schlager, C
    Fitzner, J
    CONFERENCE RECORD OF THE THIRTY-SECOND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1998, : 1730 - 1734
  • [3] System-level modeling environment: MLDesigner
    Agarwal, Ankur
    Iskander, Cyril-Daniel
    Shankar, Ravi
    Haraza-Lup, Georgiana
    2008 2ND ANNUAL IEEE SYSTEMS CONFERENCE, 2008, : 396 - +
  • [4] High-level modeling of communication-centric applications: Extensions to a system-level design and virtual prototyping tool
    Genius, Daniela
    Apvrille, Ludovic
    Li, Letitia W.
    MICROPROCESSORS AND MICROSYSTEMS, 2019, 67 : 117 - 130
  • [5] Interface synthesis in heterogeneous system-level DSP design tools
    Pino, JL
    Williamson, MC
    Lee, EA
    1996 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, CONFERENCE PROCEEDINGS, VOLS 1-6, 1996, : 1268 - 1271
  • [6] Advanced SoC Virtual Prototyping for System-Level Power Planning And Validation
    Mischkalla, Fabian
    Mueller, Wolfgang
    2014 24TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), 2014,
  • [7] System-Level Design and Virtual Prototyping of a Telecommunication Application on a NUMA Platform
    Genius, Daniela
    Apvrille, Ludovic
    PROCEEDINGS OF THE 2018 13TH INTERNATIONAL SYMPOSIUM ON RECONFIGURABLE COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC), 2018,
  • [8] System level prototyping for embedded networking applications
    Loy, D
    Murase, A
    Doederlein, A
    12TH INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS, 2000, : 12 - 16
  • [9] SYSTEM-LEVEL SUPPORT FOR DEPENDABLE DISTRIBUTED APPLICATIONS
    KROEGER, R
    NETT, E
    LECTURE NOTES IN COMPUTER SCIENCE, 1991, 563 : 178 - 181
  • [10] System-level simulation environment for system-on-chip design
    Darmstadt Univ of Technology, Darmstadt, Germany
    Proc Annu IEEE Int ASIC Conf Exhib, (58-62):