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- [17] Design-for-test of asynchronous Networks-On-Chip PROCEEDINGS OF THE 2006 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2006, : 163 - +
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- [19] From design-for-test to design-for-debug-and-test: Analysis of requirements and limitations for 1149.1 17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1999, : 473 - 480