ANALYSIS OF D-TYPE FLIP-FLOP FREQUENCY-CHANGERS

被引:0
|
作者
SHAW, DI [1 ]
BENNETT, JC [1 ]
CLEMENTS, AM [1 ]
机构
[1] UNIV SHEFFIELD,DEPT ELECTR ENGN,SHEFFIELD S1 3JD,S YORKSHIRE,ENGLAND
关键词
Flip-flops; Memories;
D O I
10.1049/el:19901290
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel approach using Fourier analysis to model a digital system, in this case a ‘D type’ flip-flop, is presented. An analysis of the flip-flop using mathematics, with a graphical example to illustrate the logic operation of the flip flop as a frequency changer, in this case a down-convertor, is presented. This type of analysis could prove invaluable in modelling digital phase locked loops and frequency synthesisers. © 1990, The Institution of Electrical Engineers. All rights reserved.
引用
收藏
页码:1995 / 1997
页数:3
相关论文
共 50 条
  • [21] Comparative study of static and dynamic D-type flip-flop circuits using InPHBT's
    Yeo, HS
    Burm, J
    Kim, SI
    Min, BG
    Ju, CW
    [J]. PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 352 - 355
  • [22] A 80-Gbit/s D-type flip-flop circuit using InPHEMT technology
    Suzuki, T
    Takahashi, T
    Hirose, T
    Takigawa, M
    [J]. GAAS IC SYMPOSIUM - 25TH ANNUAL TECHNICAL DIGEST 2003, 2003, : 165 - 168
  • [23] 40-Gbit/s D-type flip-flop and multiplexer circuits using InPHEMT
    Suzuki, T
    Kano, H
    Nakasha, Y
    Takahashi, T
    Imanishi, K
    Ohnishi, H
    Watanabe, Y
    [J]. 2001 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2001, : 291 - 294
  • [24] 40-Gbit/s D-type flip-flop and multiplexer circuits using InPHEMT
    Suzuki, T
    Kano, H
    Nakasha, Y
    Takahashi, T
    Imanishi, K
    Ohnishi, H
    Watanabe, Y
    [J]. 2001 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3, 2001, : 595 - 598
  • [25] An energy efficient half-static clock-gating D-type flip-flop
    Tam, Wing-Shan
    Wong, Oi-Ying
    Mok, Ka-Yan
    Kok, Chi-Wah
    Wong, Hei
    [J]. EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS, 2007, : 325 - 328
  • [26] AN ENERGY EFFICIENT HALF-STATIC CLOCK-GATING D-TYPE FLIP-FLOP
    Tam, Wing-Shan
    Wong, Oi-Ying
    Mok, Ka-Yan
    Kok, Chi-Wah
    Wong, Hei
    [J]. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2010, 19 (03) : 635 - 654
  • [27] A 22-Gbit/s static decision IC made with a novel D-type flip-flop
    Narahara, K
    Otsuji, T
    Tokumitsu, M
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 1999, E82C (03) : 559 - 561
  • [28] 40 Gbit/s master-slave D-type flip-flop in InP DHBT technology
    Kasbari, A
    André, P
    Godin, J
    Konczykowska, A
    [J]. ELECTRONICS LETTERS, 2002, 38 (07) : 330 - 331
  • [29] Design of high speed master-slave D-type flip-flop in InP DHBT technology
    Kasbari, AE
    André, P
    Konczykowska, A
    Riet, M
    Blayac, S
    Ouslimani, H
    Godin, J
    [J]. 2002 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3, 2002, : 1057 - 1060
  • [30] 13GB/S D-TYPE FLIP-FLOP IC USING GAAS-MESFETS
    OHHATA, M
    YAMANE, Y
    ENOKI, T
    SUGITANI, S
    KATO, N
    HAGIMOTO, K
    HIRAYAMA, M
    [J]. ELECTRONICS LETTERS, 1990, 26 (14) : 1039 - 1041