Impact of Gate Length and Doping Variation on the DC and Analog/RF Performance of sub - 3nm Stacked Si Gate-All-Around Nanosheet FET

The nanosheet Field Effect Transistors (FETs) are the promising device architecture for sub - 5nm technology node as per the International Roadmap for Devices and Systems (IRDS) 2020 and has attracted the semiconductor industry as the key device architecture for upcoming low power to high performance applications. To contribute to the growth of this continuously evolving technology, the impact of key device design parameter namely gate length (Lg) and process parameters namely source/drain (S/D) doping (NSD) and channel doping (NCH) on the DC and analog/RF performance of gate-stack based Si gate-all-around (GAA) stacked nanosheet FETs have been explored. Simulation result shows that as we downscale the Lg from 30nm to 10nm, the short channel effects (SCEs) deteriorates the device performance significantly by reducing the threshold voltage (Vth) thereby increasing the OFF-current (Ioff) by 4 orders and degrading the sub-threshold swing (SS) and drain induced barrier lowering (DIBL). However, the ON-current (Ion), ON-current to OFF-current ratio (Ion/Ioff), intrinsic delay and analog/RF performance improves at shorter Lg. Higher NSD results in improved driving capability and analog performance of the device. However, Ioff, Ion/Ioff ratio, SS and DIBL degrades with higher NSD. Higher channel doping poses a solution to circumvent the SCEs in aggressively scaled devices, however, it causes scattering thereby reducing the mobility of the carriers. So, the doping should be chosen wisely to get the desired Vth and other performance parameters.