A Gated Clock Scheme for Low Power Testing of Logic Cores

被引：0
|
作者：
Yannick Bonhomme
Patrick Girard
Loïs Guiller
Christian Landrault
Serge Pravossoudovitch
Arnaud Virazel
机构：
[1] UMR 5506/Université Montpellier II / CNRS,Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
[2] Saclay,CEA
[3] Mountain View,LIST
来源：
Journal of Electronic Testing | 2006年 / 22卷
关键词：
low power design; low power test; test-per-scan; test-per-clock;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Test power is now a big concern in large core-based systems. In this paper, we present a general approach for minimizing power consumption during test of integrated circuits or embedded cores. The proposed low power/energy technique is based on a gated clock scheme that can be used in a test-per-scan or a test-per-clock environment. The idea is to reduce the clock rate on the scan path (test-per-scan) or the test pattern generator (test-per-clock) without increasing the test time. Numerous advantages can be found in applying such a technique.
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页码：89 / 99
页数：10
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