Energy efficient hybrid full adder design for digital signal processing in nanoelectronics

In recent years, there has been a growing interest in energy efficient VLSI designs for portable devices. Full adder cell is one of the most widely used and important blocks of arithmetic units that are in many digital signal processors. The quest to reach low energy consumption, and high noise immunity in the nanoscale regime, directed this work for discovering a new low-power and noise immune full adder cell. In this paper, a full adder with an innovative hybrid structure of pass-transistor and complementary styles is proposed based on carbon nanotube field effect transistor (CNFET). CNFET as one of the alternative nanodevices is the most feasible option to replace MOSFET technology for production by the early 2020, from industry perspective. The proposed full adder as well as the most relevant state-of-the-art designs are evaluated for different parameters, such as delay, power dissipation, and energy consumption over two different test-bed scenarios. In the first scenario, full adder cells are compared for different operating conditions such as different operating frequency, load capacitors, and supply voltages. In the second scenario, full adder cells are embedded and evaluated in 4-operands carry save adder with the final ripple carry adder in 4 and 8 bit lengths. These evaluations have been carried out using Synopsis HSPICE and the Stanford CNFET model for the 16 nm technology node. The proposed full adder leads to the average energy consumption improvements of 37% and 43% in 4-bit and 8-bit structures, respectively, as compared to the other existing designs. Also simulation results indicated that the proposed design is more immune against noises compared to the other designs.