Schmitter trigger-based single-ended stable 7T SRAM cell

In this paper, a schmitt trigger-based single-sided 7T stable SRAM is proposed for ultra-low energy and near-threshold operation, which supports a bit interleaving scheme. The proposed ST-7T SRAM design improves the WSNM (Write Static Noise Margin) and RSNM (Read Static Noise Margin) and consumes less energy. Moreover, obtain high read strength by utilizing a single-sided ST (schmitt trigger) inverter. Furthermore, write ability is also enhanced by applying an ST inverter write assist scheme (Negative VWWL technique), which can limit the tripping voltage of the ST inverter circuit. The PST-7T (Proposed ST-7T) circuit minimizes the read power by 49.96%, write power by 39.27%, and leakage power by 39.17% compared to conventional-6T SRAM. The RSNM and WSNM of the proposed SRAM circuit are enhanced by 66.28% and 18.97% compared to conventional-6T SRAM. The write energy and read energy utilization are also lowered by 14.87% and 14.19% compared to the SE7T SRAM cell.