Design and analysis of single-ended robust low power 8T SRAM cell

This paper is based on the observation of 8T single ended static random access memory (SRAM) and two techniques for reducing the sub threshold leakage current, power consumption are examined. In the first technique, effective supply voltage and ground node voltages are changed using a dynamic variable voltage level technique(VVL). In the second technique power supply is scaled down. This 8T SRAM cell uses one word line, two bitlinesand a transmission gate. Simulations and analytical results show that when the two techniques combine the new SRAM cell has correct read and write operation and also the cell contains 55.6% less leakage and the dynamic power is 98.8% less than the 8T single ended SRAM cell. Simulations are performed using cadence virtuoso tool at 45nm technology.