Gate Drain Underlapping: A Performance Enhancer For HD-GAA-TFET

In this paper, the influence of gate-drain underlapping (GDU) and hetero gate dielectric (HD) has been studied on the switching performance, and parasitic capacitance of gate all around tunnel FET i.e. GAA-TFET. Results thus obtained reveals that via GDU the major impediments of TFET i.e. ambipolar conduction can be suppressed. However, the asymmetric dielectric as gate oxide or HD engineering enhances the ON-state current of TFET. Consequently, by amalgamating both GDU and HD engineering schemes onto GAA-TFET have collectively resulted into suppressed IAMB along with high I-ON. A comparative analysis of GDU-GAA-TFET, HD-GAA-TFET, and GDU-HD-GAA-TFET with GAA-TFET has been done in terms of switching parameters, bias dependent parasitic capacitance and RF FOMs. Results indicate that GDU-HD-GAA-TFET shows better device performance in terms of the threshold voltage, subthreshold swing SS, and I-ON/I-OFF ratio in comparison to its conventional counterparts. However, an affordable degradation in parasitic capacitance is obtained for GDU-HD-GAA-TFET due to the high-k material near source side that is used to enhance the I-ON and I-ON/I-OFF ratio. It is found that GDU-HD-GAA-TFET offers an I-ON/I-OFF ratio in the order of 10(13) at a SS of 25 mV/decade making it suitable for low power digital applications. (C) 2017 Elsevier Ltd. All rights reserved.