Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behavior

The goal of this work is to overcome the major impediments of tunnel FET such as the inherent ambipolar current (IAMB) and the lower ON current (ION). To suppress the IAMB, gate drain overlap (GDO) engineering scheme has been incorporated over the cylindrical gate all around TFET (GAA-TFET). However, to enhance the ION, heterogate dielectrics (HD) are used in the gate oxide region. Results indicate that an appreciably reduced IAMB and significantly enhanced ION has been obtained with the amalgamation of GDO and HD, respectively, onto GAA-TFET. Further, the effect of GDO length (Lov) has also been studied. Quantitative analysis of ambipolarity factor “α” reveals that at large Lov, “α” improves. It is found that GDO degrades the high-frequency (HF) performance such as cutoff frequency (fT) of the device, because of the enhanced parasitic capacitances. To surpass the deterioration at HF caused by GDO, the dielectric over GDO region has been altered, and it has been analyzed that by inserting a material of low-dielectric constant (k = 1) and parasitic capacitances of the device reduces, resulting into enhancement in fT. Moreover, the low-k dielectric inserted over Lov reduces the IAMB supplementary, along with enhanced fT. Suppressed IAMB and enhanced fT of GDO–HD–GAA-TFET with low-k dielectric over Lov make it adequate for application in HF and digital circuitry.