Cellular array-based delay-insensitive asynchronous circuits design and test for nanocomputing systems

This paper presents the design, layout, and testability analysis of delay-insensitive circuits on cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a signal path does not affect the correctness of circuit behavior. The combination of delay-in sensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems. In the approach proposed in this paper the circuit expressions Corresponding to a design are first converted into Reed-Muller forms and then implemented using delay-insensitive Reed-Muller cells. The design and layout of the Reed-Muller cell using primitives has been described in detail. The effects of stuck-at faults in both delay-insensitive primitives and gates have been analyzed. Since circuits implemented in Reed-Muller forms constructed by the Reed-Muller cells can be easily tested offline, the proposed approach for delay-insensitive circuit design improves a circuit's testability. Potential physical implementation of cellular arrays and its area overhead are also discussed.