HIERARCHICAL DESIGN OF DELAY-INSENSITIVE SYSTEMS

被引：5
|
作者：
LAM, PN
LI, HF
机构：
[1] Concordia Univ, , Que
来源：
IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES | 1990年 / 137卷 / 01期
关键词：
D O I：
10.1049/ip-e.1990.0004
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A set of building blocks is presented for the hierarchical design of delay-insensitive systems. It consists of delay-insensitive (DI) building blocks and hybrid (non-DI) building blocks. An extended signal transition graph (STG) model is used for circuit specification and analysis. It permits the clear specification of delay-insensitive circuits, distinguishing between environment/module behaviour and DI/non-DI components. A hierarchical composition procedure is described for the composition of deterministic STG specifications. As an example, a circuit for distributed mutual exclusion is designed and implemented.
引用
收藏
页码：41 / 56
页数：16
相关论文
共 50 条
  • [1] DELAY-INSENSITIVE CIRCUITS - AN ALGEBRAIC APPROACH TO THEIR DESIGN
    JOSEPHS, MB
    UDDING, JT
    [J]. LECTURE NOTES IN COMPUTER SCIENCE, 1990, 458 : 342 - 366
  • [2] Modular Timing Constraints for Delay-Insensitive Systems
    Park, Hoon
    He, Anping
    Roncken, Marly
    Song, Xiaoyu
    Sutherland, Ivan
    [J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2016, 31 (01) : 77 - 106
  • [3] Modular Timing Constraints for Delay-Insensitive Systems
    Hoon Park
    Anping He
    Marly Roncken
    Xiaoyu Song
    Ivan Sutherland
    [J]. Journal of Computer Science and Technology, 2016, 31 : 77 - 106
  • [4] Universal delay-insensitive systems with buffering lines
    Lee, J
    Peper, F
    Adachi, S
    Mashiko, S
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2005, 52 (04) : 742 - 754
  • [5] Quasi delay-insensitive bus for fully asynchronous systems
    Molina, PA
    Cheung, PYK
    Bormann, DS
    [J]. ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 189 - 192
  • [6] DESIGN OF A DELAY-INSENSITIVE MULTIPLY-ACCUMULATE UNIT
    NIELSEN, CD
    MARTIN, AJ
    [J]. INTEGRATION-THE VLSI JOURNAL, 1993, 15 (03) : 291 - 311
  • [7] DELAY-INSENSITIVE MULTIRING STRUCTURES
    SPARSO, J
    STAUNSTRUP, J
    [J]. INTEGRATION-THE VLSI JOURNAL, 1993, 15 (03) : 313 - 340
  • [8] A quasi delay-insensitive bus proposal for asynchronous systems
    Molina, PA
    Cheung, PYK
    [J]. THIRD INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 1997, : 126 - 139
  • [9] Controllable delay-insensitive processes
    Josephs, Mark B.
    Kapoor, Hemangee K.
    [J]. FUNDAMENTA INFORMATICAE, 2007, 78 (01) : 101 - 130
  • [10] AN ALGEBRA FOR DELAY-INSENSITIVE CIRCUITS
    JOSEPHS, MB
    UDDING, JT
    [J]. LECTURE NOTES IN COMPUTER SCIENCE, 1991, 531 : 343 - 352
12345