HIERARCHICAL DESIGN OF DELAY-INSENSITIVE SYSTEMS

被引：5
|
作者：
LAM, PN
LI, HF
机构：
[1] Concordia Univ, , Que
来源：
IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES | 1990年 / 137卷 / 01期
关键词：
23;
D O I：
10.1049/ip-e.1990.0004
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A set of building blocks is presented for the hierarchical design of delay-insensitive systems. It consists of delay-insensitive (DI) building blocks and hybrid (non-DI) building blocks. An extended signal transition graph (STG) model is used for circuit specification and analysis. It permits the clear specification of delay-insensitive circuits, distinguishing between environment/module behaviour and DI/non-DI components. A hierarchical composition procedure is described for the composition of deterministic STG specifications. As an example, a circuit for distributed mutual exclusion is designed and implemented.
引用
收藏
页码：41 / 56
页数：16
相关论文
共 50 条
  • [31] Chain: A delay-insensitive chip area interconnect
    Bainbridge, J
    Furber, S
    [J]. IEEE MICRO, 2002, 22 (05) : 16 - 23
  • [32] Delay-insensitive computation in asynchronous cellular automata
    Lee, J
    Adachi, S
    Peper, F
    Mashiko, S
    [J]. JOURNAL OF COMPUTER AND SYSTEM SCIENCES, 2005, 70 (02) : 201 - 220
  • [33] TRANSLATING CONCURRENT PROGRAMS INTO DELAY-INSENSITIVE CIRCUITS
    BRUNVAND, E
    SPROULL, RF
    [J]. 1989 IEEE INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1989, : 262 - 265
  • [34] Novel Approaches for Efficient Delay-Insensitive Communication
    Huemer, Florian
    Steininger, Andreas
    [J]. JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS, 2019, 9 (02)
  • [35] Membership test logic for delay-insensitive codes
    Piestrak, SJ
    [J]. ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS - FOURTH INTERNATIONAL SYMPOSIUM, 1998, : 194 - 204
  • [36] A FORMAL APPROACH TO DESIGNING DELAY-INSENSITIVE CIRCUITS
    EBERGEN, JC
    [J]. DISTRIBUTED COMPUTING, 1991, 5 (03) : 107 - 119
  • [37] DELAY-INSENSITIVE PIPELINED COMMUNICATION ON PARALLEL BUSES
    BLAUM, M
    BRUCK, J
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1995, 44 (05) : 660 - 668
  • [38] NORMAL-FORM IN A DELAY-INSENSITIVE ALGEBRA
    GROENBOOM, R
    JOSEPHS, MB
    LUCASSEN, PG
    UDDING, JT
    [J]. ASYNCHRONOUS DESIGN METHODOLOGIES, 1993, 28 : 57 - 70
  • [39] Diagrammatic reasoning for delay-insensitive asynchronous circuits
    [J]. Ghica, D.R., 1600, Springer Verlag (7860 LNCS):
  • [40] A Delay-Insensitive Address-Event Link
    Lin, Joseph
    Boahen, Kwabena
    [J]. ASYNC: 2009 15TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, 2009, : 50 - +
12345