Modular Timing Constraints for Delay-Insensitive Systems

被引:13
|
作者
Park, Hoon [1 ,2 ]
He, Anping [3 ]
Roncken, Marly [1 ]
Song, Xiaoyu [2 ]
Sutherland, Ivan [1 ]
机构
[1] Portland State Univ, Asynchronous Res Ctr, Portland, OR 97201 USA
[2] Portland State Univ, Dept Elect & Comp Engn, Portland, OR 97201 USA
[3] Lanzhou Univ, Sch Informat Sci & Engn, Lanzhou 730000, Peoples R China
基金
中国国家自然科学基金;
关键词
self-timed circuit; delay-insensitive system; model checking; timing analysis; design pattern; LOW-POWER; CIRCUITS; VERIFICATION; MODEL;
D O I
10.1007/s11390-016-1613-y
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component's gate-level circuit implementation obeys the component's handshake protocol specification. Because the handshake protocols are delay-insensitive, self-timed systems built using ARCtimer-verified components are also delay-insensitive. By carefully considering time locally, we can ignore time globally. ARCtimer comes early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis (STA) code to validate and enforce the component's constraints in any self-timed system built using the library. The library descriptions of a handshake component's circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools. In addition to presenting new work and discussing related work, this paper identifies critical choices and explains what modular timing verification entails and how it works.
引用
收藏
页码:77 / 106
页数:30
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