Embedding universal delay-insensitive circuits in asynchronous cellular spaces

被引:0
|
作者
Lee, J
Adachi, S
Peper, F
Morita, K
机构
[1] Commun Res Labs, Nanotechnol Grp, Nishi Ku, Kobe, Hyogo 6512492, Japan
[2] Hiroshima Univ, Dept Informat Engn, Higashihiroshima 7398527, Japan
关键词
D O I
暂无
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
Asynchronous Cellular Automata (ACA) are cellular automata which allow cells to be updated at times that are random and independent of each other. Due to their unpredictable behavior, ACA are usually dealt with by simulating a timing mechanism that forces all cells into synchronicity. Though this allows the use of well-established synchronous methods to conduct computations, it comes at the price of an increased number of cell states. This paper presents a more effective approach based on a 5-state ACA with von Neumann neighborhood that uses rotation- and reflection-symmetric transition rules to describe the interactions between cells. We achieve efficient computation on this model by embedding so-called Delay-Insensitive circuits in it, a type of asynchronous circuits in which signals may be subject to arbitrary delays, without this being an obstacle to correct operation. Our constructions not only imply the computational universality of the proposed cellular automaton, but also allow the efficient use of its massive parallelism, in the sense that the circuits operate in parallel and there are no signals running around indefinitely in the circuits in the absence of input.
引用
收藏
页码:295 / 320
页数:26
相关论文
共 50 条
  • [1] Diagrammatic reasoning for delay-insensitive asynchronous circuits
    [J]. Ghica, D.R., 1600, Springer Verlag (7860 LNCS):
  • [2] Delay-insensitive computation in asynchronous cellular automata
    Lee, J
    Adachi, S
    Peper, F
    Mashiko, S
    [J]. JOURNAL OF COMPUTER AND SYSTEM SCIENCES, 2005, 70 (02) : 201 - 220
  • [3] Universal delay-insensitive circuits with bidirectional and buffering lines
    Lee, J
    Peper, F
    Adachi, S
    Morita, K
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2004, 53 (08) : 1034 - 1046
  • [4] An Automated Design Flow Framework for Delay-Insensitive Asynchronous Circuits
    Thian, Ross
    Caley, Landon
    Arthurs, Aaron
    Hollosi, Brent
    Di, Jia
    [J]. 2012 PROCEEDINGS OF IEEE SOUTHEASTCON, 2012,
  • [5] On the realisation of delay-insensitive asynchronous circuits with CMOS ternary logic
    Mariani, R
    Roncella, R
    Saletti, R
    Terreni, P
    [J]. THIRD INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 1997, : 54 - 62
  • [6] Synthesis of nanoelectronic circuits on delay-insensitive cellular arrays
    Di, J
    Lala, PK
    Vasudevan, D
    [J]. DELTA 2006: THIRD IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, 2006, : 149 - +
  • [7] Cellular array-based delay-insensitive asynchronous circuits design and test for nanocomputing systems
    Di, Jia
    Lala, Parag K.
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2007, 23 (2-3): : 175 - 192
  • [8] Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems
    Jia Di
    Parag K. Lala
    [J]. Journal of Electronic Testing, 2007, 23 : 175 - 192
  • [9] AN ALGEBRA FOR DELAY-INSENSITIVE CIRCUITS
    JOSEPHS, MB
    UDDING, JT
    [J]. LECTURE NOTES IN COMPUTER SCIENCE, 1991, 531 : 343 - 352
  • [10] The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits
    Manohar, Rajit
    Moses, Yoram
    [J]. 2017 23RD IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC), 2017, : 102 - 109