Energy Optimization in 3D Networks-on-Chip through Dynamic Voltage Scaling technique

Networks-on-Chips (NoCs) consume the large fraction of the whole system energy budget. Three-dimensional NoCs overcome the communication demands as a viable architecture in many-core systems, outperform 2D NoCs in terms of area, latency, performance and scalability, however, 3D NoCs consume high power even more than 2D NoCs. Using the voltage scaling technique in routers and links can significantly improve energy saving. Unfortunately, voltage level reduction compromises the latency and the communication reliability. As emerging applications can tolerate inaccuracy in the output and due to the latency reduction in 3D NoCs, Dynamic Voltage Scaling (DVS) technique is applied to the links and routers of 3D NoC in facing with error tolerance communications. Therefore, energy efficiency and the performance are significantly improved in 3D NoC while outputs are within an acceptable variance. Simulation results indicate that the described method improves on average the energy efficiency 27% across different PARSEC benchmarks.