Abetting Planned Obsolescence by Aging 3D Networks-on-Chip

被引:0
|
作者
Das, Sourav [1 ]
Basu, Kanad [2 ]
Doppa, Janardhan Rao [1 ]
Pande, Partha Pratim [1 ]
Karri, Ramesh [2 ]
Chakrabarty, Krishnendu [3 ]
机构
[1] Washington State Univ, Sch EECS, Pullman, WA 99164 USA
[2] NYU, Dept ECE, Brooklyn, NY USA
[3] Duke Univ, Dept ECE, Durham, NC USA
基金
美国国家科学基金会;
关键词
3D NoC; Latency; Energy; EDP; TSV; Electromigration; Security; Hardware Attack; NBTI; GENERATION;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We set up a security analysis framework by aging the Network-on-Chip (NoC) to study planned obsolescence by the original equipment manufacturer (OEM). An NoC is the communication backbone in a manycore System-on-Chip (SoC). Planned obsolescence may adopt any vulnerability in the NoC to cause the SoC to fail. We show how an OEM can craft workloads to generate electromigration-induced stress and crosstalk noise in TSV-based vertical links in the NoC to hasten failure. We analyzed three malicious workloads and confirm that a crafted workload that injects 3-10% more traffic on to a few selected critical vertical links can shorten the lifetime of the NoC by 11%-25% averaged over the benchmarks considered in this work.
引用
收藏
页数:8
相关论文
共 50 条
  • [1] An enhanced planned obsolescence attack by aging networks-on-chip
    Zhao, Yinyuan
    Wang, Xiaohang
    Jiang, Yingtao
    Wang, Liang
    Singh, Amit Kumar
    Huang, Letian
    Yang, Mei
    [J]. JOURNAL OF SYSTEMS ARCHITECTURE, 2021, 117
  • [2] The Benefits of 3D Networks-on-Chip as shown with LDPC Decoding
    Mineo, Christopher
    Davis, W. Rhett
    [J]. 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, : 89 - 96
  • [3] Efficient routing techniques in heterogeneous 3D Networks-on-Chip
    Agyeman, Michael Opoku
    Ahmadinia, Ali
    Shahrabi, Alireza
    [J]. PARALLEL COMPUTING, 2013, 39 (09) : 389 - 407
  • [4] 3D Optical Networks-on-chip (NoC) for Multiprocessor Systems-on-chip (MPSoC)
    Ye, Yaoyao
    Duan, Lian
    Xu, Jiang
    Ouyang, Jin
    Hung, Mo Kwai
    Xie, Yuan
    [J]. 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, : 83 - +
  • [5] 3D Networks-on-Chip mapping targeting minimum signal TSVs
    Ding, Hui
    Gu, Huaxi
    Yang, Yintang
    Fan, Dongrui
    [J]. IEICE ELECTRONICS EXPRESS, 2013, 10 (18):
  • [6] Design of Application-Specific 3D Networks-on-Chip Architectures
    Yan, Shan
    Lin, Bill
    [J]. 2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2008, : 142 - 149
  • [7] A Systematic Generation of Optimized Heterogeneous 3D Networks-on-Chip Architecture
    Agyeman, Michael Opoku
    Ahmadinia, Ali
    [J]. 2013 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS), 2013, : 79 - 83
  • [8] NoCDepend: A flexible and scalable Dependability Technique for 3D Networks-on-Chip
    Hollstein, Thomas
    Azad, Siavoosh Payandeh
    Kogge, Thilo
    Ying, Haoyuan
    Hofmann, Klaus
    [J]. 2015 IEEE 18TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS 2015), 2015, : 75 - 78
  • [9] 3-D topologies for networks-on-chip
    Pavlidis, Vasilis F.
    Friedman, Eby G.
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (10) : 1081 - 1090
  • [10] 3-D topologies for networks-on-chip
    Pavlidis, Vasilis F.
    Friedman, Eby G.
    [J]. IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2006, : 285 - +