Abetting Planned Obsolescence by Aging 3D Networks-on-Chip

被引：0

作者：

Das, Sourav ^{[1
]}

Basu, Kanad ^{[2
]}

Doppa, Janardhan Rao ^{[1
]}

Pande, Partha Pratim ^{[1
]}

Karri, Ramesh ^{[2
]}

Chakrabarty, Krishnendu ^{[3
]}

机构：

[1] Washington State Univ, Sch EECS, Pullman, WA 99164 USA

[2] NYU, Dept ECE, Brooklyn, NY USA

[3] Duke Univ, Dept ECE, Durham, NC USA

来源：

2018 TWELFTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS) | 2018年

基金：

美国国家科学基金会;

关键词：

3D NoC; Latency; Energy; EDP; TSV; Electromigration; Security; Hardware Attack; NBTI; GENERATION;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We set up a security analysis framework by aging the Network-on-Chip (NoC) to study planned obsolescence by the original equipment manufacturer (OEM). An NoC is the communication backbone in a manycore System-on-Chip (SoC). Planned obsolescence may adopt any vulnerability in the NoC to cause the SoC to fail. We show how an OEM can craft workloads to generate electromigration-induced stress and crosstalk noise in TSV-based vertical links in the NoC to hasten failure. We analyzed three malicious workloads and confirm that a crafted workload that injects 3-10% more traffic on to a few selected critical vertical links can shorten the lifetime of the NoC by 11%-25% averaged over the benchmarks considered in this work.

引用

页数：8

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