The Benefits of 3D Networks-on-Chip as shown with LDPC Decoding

被引:0
|
作者
Mineo, Christopher [1 ]
Davis, W. Rhett [1 ]
机构
[1] N Carolina State Univ, Dept Elect & Comp Engn, Raleigh, NC 27695 USA
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中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this work we describe our network-on-chip (NoC) simulator, which fills the gap between architectural level and circuit level NoC simulation. The core is a fast, high level transaction-based NoC simulator, which accesses carefully compiled power, timing, and area models for basic NoC componets built from detailed circuit simulation. It makes use of the architectural evaluator, which performs a detailed global interconnect analysis within the framework of industry-standard design tools. Using low density parity check decoding as a test vehicle, the NoC simulator is used in an NoC design study comparing 2D and 3D integrated circuits, and shows a method by which on-chip networks can be optimized.
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页码:89 / 96
页数:8
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