Die-to-Wafer (D2W) Processing and Reliability for 3D Packaging of Advanced Node Logic

被引：6
|
作者：
England, Luke [1 ]
Fisher, Daniel [1 ]
Rivera, Katie [1 ]
Guthrie, Bill [1 ]
Kuo, Ping-Jui [2 ]
Lee, Chang-Chi [2 ]
Hsu, Che-Ming [2 ]
Min, Fan-Yu [2 ]
Kang, Kuo-Chang [2 ]
Weng, Chen-Yuan [2 ]
机构：
[1] GLOBALFOUNDRIES, Austin, TX 78735 USA
[2] ASE, Kaohsiung, Taiwan
来源：
2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2019年
关键词：
3D Packaging; TSV; Die-to-Wafer; D2W; Chip-to-Wafer; C2W;
D O I：
10.1109/ECTC.2019.00096
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In order to support emerging applications such as machine learning, where large amounts of fast access memory are required, the use of 3D packaging is inevitable. Previous work on 3D packaging with advanced node logic has shown that the technology is ready for implementation. In this paper, GF and ASE have demonstrated a Die-to-Wafer (D2W) process using 50um thickness logic wafers as the base. The 3D package also includes integrated thermal structures for heat removal from the base logic die. The process flow will be reviewed in detail, and challenges that were faced and overcome will be discussed. Reliability performance of the 3D package will also be reported. In addition, extensive thermal modeling was completed to understand the impact of two competing solutions for heat removal, which will also be reviewed in detail.
引用
收藏
页码：600 / 606
页数：7
相关论文
共 50 条
  • [41] Design and Architecture Definition for Advanced 3D Fan-Out Wafer-Level Packaging
    Bhangaonkar, Karan
    Sankarasubramanian, Santosh
    Journal of Microelectronics and Electronic Packaging, 2024, 21 (03): : 59 - 66
  • [42] Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last
    Shen, Jiayi
    Liu, Chang
    Hoshi, Tadaaki
    Sinoda, Atsushi
    Kino, Hisashi
    Tanaka, Tetsu
    Mariappan, Murugesan
    Koyanagi, Mitsumasa
    Fukushima, Takafumi
    2023 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE, 3DIC, 2023,
  • [43] Die to Wafer/Die DBI Hybrid Bonding for a True 3D Interconnect
    Haba, Belgacem
    PROCEEDINGS OF 2019 6TH INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D), 2019, : 18 - 18
  • [44] The roles of "3d/2d" and "3d/3d" topography simulators in virtual wafer fabs
    Cale, TS
    Merchant, TP
    Borucki, LJ
    SEMICONDUCTOR PROCESS AND DEVICE PERFORMANCE MODELLING, 1998, 490 : 201 - 212
  • [45] TSV inspection in 3D advanced packaging applications
    Asgari, Reza
    SOLID STATE TECHNOLOGY, 2012, 55 (05) : 24 - +
  • [46] Advanced Fault Isolation Techniques for 3D Packaging
    Chen, Y.
    Lai, P.
    Shi, Q.
    PROCEEDINGS OF THE 2016 IEEE 23RD INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2016, : 212 - 215
  • [47] Development of TSV Interposer with 300 mm Wafer for 3D Packaging
    Yoshimi, Seiichi
    Fujimoto, Koji
    Akazawa, Miyuki
    Matsumoto, Hidenobu
    Mawatari, Hiroshi
    Suzuki, Kousuke
    Itoh, Toshihiro
    Maeda, Ryutaro
    2013 SYMPOSIUM ON DESIGN, TEST, INTEGRATION AND PACKAGING OF MEMS/MOEMS (DTIP), 2013,
  • [48] 3D Wafer Level Packaging: Processes and Materials for Through-Silicon Vias and Thin Die Embedding
    Soussan, Philippe
    Tezcan, Deniz Sabuncuoglu
    Iker, Francois
    Ruythooren, Wouter
    Majeed, Bivragh
    Swinnen, Bart
    Ruytooren, Wouter
    Beyne, Eric
    MATERIALS AND TECHNOLOGIES FOR 3-D INTEGRATION, 2009, 1112 : 43 - 53
  • [49] Challenges of High-Robustness Self-Assembly with Cu/Sn-Ag Microbump Bonding for Die-to-Wafer 3D Integration
    Suzuki, Taku
    Asami, Kazushi
    Kitamura, Yasuhiro
    Fukushima, Takafumi
    Nagai, Chisato
    Bea, Jichoel
    Sato, Yutaka
    Murugesan, Mariappan
    Lee, Kang-wook
    Koyanagi, Mitsumasa
    2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 342 - 347
  • [50] Silicon Reliability Characterization of Intel's Foveros 3D Integration Technology for Logic-on-Logic Die Stacking
    Prasad, Chetan
    Chugh, Sunny
    Greve, Hannes
    Ho, I-chen
    Kabir, Enamul
    Lin, Cheyun
    Maksud, Mahjabin
    Novak, Steven R.
    Orr, Benjamin
    Park, Keun Woo
    Schmitz, Anthony
    Zhang, Zhizheng
    Bai, Peng
    Ingerly, Doug B.
    Armagan, Emre
    Wu, Hsinwei
    Stover, Patrick
    Hibbeler, Lance
    O'Day, Michael
    Pantuso, Daniel
    2020 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2020,
12345