Die-to-Wafer (D2W) Processing and Reliability for 3D Packaging of Advanced Node Logic

被引：6

作者：

England, Luke ^{[1
]}

Fisher, Daniel ^{[1
]}

Rivera, Katie ^{[1
]}

Guthrie, Bill ^{[1
]}

Kuo, Ping-Jui ^{[2
]}

Lee, Chang-Chi ^{[2
]}

Hsu, Che-Ming ^{[2
]}

Min, Fan-Yu ^{[2
]}

Kang, Kuo-Chang ^{[2
]}

Weng, Chen-Yuan ^{[2
]}

机构：

[1] GLOBALFOUNDRIES, Austin, TX 78735 USA

[2] ASE, Kaohsiung, Taiwan

来源：

2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2019年

关键词：

3D Packaging; TSV; Die-to-Wafer; D2W; Chip-to-Wafer; C2W;

D O I：

10.1109/ECTC.2019.00096

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In order to support emerging applications such as machine learning, where large amounts of fast access memory are required, the use of 3D packaging is inevitable. Previous work on 3D packaging with advanced node logic has shown that the technology is ready for implementation. In this paper, GF and ASE have demonstrated a Die-to-Wafer (D2W) process using 50um thickness logic wafers as the base. The 3D package also includes integrated thermal structures for heat removal from the base logic die. The process flow will be reviewed in detail, and challenges that were faced and overcome will be discussed. Reliability performance of the 3D package will also be reported. In addition, extensive thermal modeling was completed to understand the impact of two competing solutions for heat removal, which will also be reviewed in detail.

引用

页码：600 / 606

页数：7

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