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- [22] Development on wafer level anisotropic conductive film for Flip-Chip interconnection 54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2004, : 155 - 158
- [23] Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2006, 29 (02): : 343 - 353
- [24] Comparison of compact on-chip inductors embedded in wafer-level package 55TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2005 PROCEEDINGS, 2005, : 1578 - 1583
- [25] A Flexible Interconnect Technology Demonstrated on a Wafer-Level Chip Scale Package 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 859 - 864
- [26] Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging IEEE Trans. Adv. Packag., 2006, 2 (343-353):
- [27] A Full E-band Low Noise Amplifier Realized by Using Novel Wafer-Level Chip Size Package Technology Suitable for Reliable Flip-chip Reflow-Soldering 2014 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS), 2014,
- [28] Room temperature stable underfill with novel latent catalyst for wafer level flip-chip packaging applications 56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, : 1905 - +
- [30] Capturing Defects in Flip-Chip CMOS Devices Using Backside EBAC Technique and SEM Microscopy ISTFA 2016: CONFERENCE PROCEEDINGS FROM THE 42ND INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, 2016, : 118 - 124