Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

被引：2
|
作者：
Huang, Pengcheng [1 ]
Chen, Shuming [1 ,2 ]
Chen, Jianjun [1 ]
机构：
[1] Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China
[2] Natl Univ Def Technol, Natl Lab Parallel & Distributed Proc, Changsha 410073, Hunan, Peoples R China
来源：
CHINESE PHYSICS B | 2016年 / 25卷 / 03期
基金：
中国国家自然科学基金;
关键词：
floating body effect; in-line stacking; silicon-on-insulator; source injection; SINGLE-EVENT TRANSIENTS; SEU RESISTANCE; SOI-SRAMS; BULK; PROPAGATION; UPSET;
D O I：
10.1088/1674-1056/25/3/036103
中图分类号：
O4 [物理学];
学科分类号：
0702 ;
摘要：
In this paper, the effect of floating body effect (FBE) on a single event transient generation mechanism in fully depleted (FD) silicon-on-insulator (SOI) technology is investigated using three-dimensional technology computer-aided design (3D-TCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carrier drift/diffusion but floating body effect (FBE) whether for positive or negative channel metal oxide semiconductor (PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking (IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.
引用
收藏
页数：7
相关论文
共 50 条
  • [41] MEASUREMENTS OF INTERFACE STATE DENSITY IN PARTIALLY-DEPLETED AND FULLY-DEPLETED SILICON-ON-INSULATOR MOSFETS BY A HIGH LOW-FREQUENCY TRANSCONDUCTANCE METHOD
    YANG, PC
    CHEN, HS
    LI, SS
    SOLID-STATE ELECTRONICS, 1992, 35 (08) : 1031 - 1035
  • [42] Supercoupling effect in short-channel ultrathin fully depleted silicon-on-insulator transistors
    Navarro, C.
    Bawedin, M.
    Andrieu, F.
    Sagnes, B.
    Martinez, F.
    Cristoloveanu, S.
    JOURNAL OF APPLIED PHYSICS, 2015, 118 (18)
  • [43] Performance evaluation of deep sub-micron, fully-depleted silicon-on-insulator (FD-SOI) transistors at low temperatures
    Yuan, J
    Patel, JU
    Vandooren, A
    2000 IEEE AEROSPACE CONFERENCE PROCEEDINGS, VOL 5, 2000, : 415 - 419
  • [44] Numerical and experimental study of a 0.25 μm fully-depleted silicon-on-insulator MOSFET:: static and dynamic radio-frequency behaviour
    Rengel, R
    Mateos, J
    Pardo, D
    González, T
    Martín, MJ
    Dambrine, G
    Danneville, F
    Raskin, JP
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2002, 17 (11) : 1149 - 1156
  • [45] Fully Depleted Strained Silicon-on-Insulator p-MOSFETs With Recessed and Embedded Silicon-Germanium Source/Drain
    Baudot, Sophie
    Andrieu, Francois
    Weber, Olivier
    Perreau, Pierre
    Damlencourt, Jean-Francois
    Barnola, Sebastien
    Salvetat, Thierry
    Tosti, Lucie
    Brevard, Laurent
    Lafond, Dominique
    Eymery, Joel
    Faynot, Olivier
    IEEE ELECTRON DEVICE LETTERS, 2010, 31 (10) : 1074 - 1076
  • [46] High-Speed Serializer for a 64 GS s(-1) Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology
    Widmann, Daniel
    Groezing, Markus
    Berroth, Manfred
    ADVANCES IN RADIO SCIENCE, 2018, 16 : 99 - 108
  • [47] 3D TCAD SIMULATION OF SINGLE-EVENT-EFFECT IN N-CHANNEL TRANSISTOR BASED ON DEEP SUB-MICRON FULLY-DEPLETED SILICON-ON-INSULATOR TECHNOLOGY
    Bi, Jinshun
    Li, Bo
    Han, Zhengsheng
    Luo, Jiajun
    Chen, Li
    Lin-Shi, Xuefang
    2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
  • [48] Total ionizing dose and single event effect response of 22 nm ultra-thin body and buried oxide fully depleted silicon-on-insulator technology
    Yin, Yanan
    Ma, Han
    Zheng, Qiwen
    Chen, Jiawei
    Duan, Xinpei
    Zhang, Pingwei
    Zhou, Xinjie
    MICROELECTRONICS RELIABILITY, 2024, 152
  • [49] Numerical simulation of single-event-transient effects on ultra-thin-body fully-depleted silicon-on-insulator transistor based on 22 nm process node
    Bi Jin-Shun
    Liu Gang
    Luo Jia-Jun
    Han Zheng-Sheng
    ACTA PHYSICA SINICA, 2013, 62 (20)
  • [50] Advantages of Faceted P-Raised Source/Drain in Fully Depleted Silicon on Insulator Technology
    Aydin, O., I
    Holt, J. R.
    Le Royer, C.
    Vanamurthy, L.
    Feudel, T.
    Heyne, T.
    Gerber, R.
    Lenski, M.
    Jansen, S.
    Utess, D.
    Klein, C.
    Peeva, A.
    Mulfinger, G. R.
    Mcardle, T. J.
    Barge, D.
    Divay, A.
    Lehmann, S.
    Smith, E.
    Peters, C.
    Sachse, J. U.
    SIGE, GE, AND RELATED COMPOUNDS: MATERIALS, PROCESSING, AND DEVICES 8, 2018, 86 (07): : 199 - 206
12345