A Comprehensive System-on-Chip Logic Diagnosis

被引:4
|
作者
Benabboud, Y. [1 ]
Bosio, A. [1 ]
Dilillo, L. [1 ]
Girard, P. [1 ]
Pravossoudovitch, S. [1 ]
Virazel, A. [1 ]
Riewer, O. [2 ]
机构
[1] Univ Montpellier 2, CNRS, LIRMM, 161 Rue Ada, F-34392 Montpellier, France
[2] STMicroelectronics, F-38920 Crolles, France
关键词
Logic Diagnosis; SoC; Fault Modeling; FAULT-DIAGNOSIS; ARBITRARY DEFECTS; TOOL;
D O I
10.1109/ATS.2010.49
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper addresses the problem of logic diagnosis of System-on-Chip (SoC). We propose a diagnosis approach based on a matching algorithm between a set of predicted failures and the set of failures observed during the test phase. The result of the diagnosis is a ranked list of suspected nets able to explain the observed failures. Experimental results show the diagnosis accuracy of the proposed approach in terms of absolute number of suspects. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.
引用
收藏
页码:237 / 242
页数:6
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