An All-digital, Cyclic and Synthesizable TDC in the ADPLL-based Clocking Digital Systems for Multidomain Power Management

被引：0

作者：

Chen, Shao-Hua ^{[1
]}

Lin, Ming-Bo ^{[1
]}

机构：

[1] Natl Taiwan Univ Sci & Technol, Dept Elect Engn, Taipei, Taiwan

来源：

Advance Materials Development and Applied Mechanics | 2014年 / 597卷

关键词：

all-digital phase-locked loop (ADPLL); dynamic voltage and frequency scaling (DVFS); system-on-chip (SoC) and time-to-digital converter (TDC);

D O I：

10.4028/www.scientific.net/AMM.597.515

中图分类号：

TH [机械、仪表工业];

学科分类号：

0802 ;

摘要：

In this paper, we propose an all-digital, cyclic and synthesizable TDC architecture, which may be used as a core block in ADPLLs to replace the analog block as a phase/frequency detector and a charge pump. Traditional designs of the DVFS scheme for multidomain power management are based on a conventional analog PLL to generate the dynamic voltage and frequency in which the use of a digital TDC eliminates the need for current sources in conventional analog PLLs.

引用

页码：515 / 518

页数：4

共 50 条

[41] A 7-GHz Fast-Lock 2-Step TDC-based All-Digital DLL for Post-DDR4 SDRAMs
Park, Dongjun
Kim, Jongsun
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
[42] An all-digital self-calibrated delay-line based temperature sensor for VLSI thermal sensing and management
Xie, Shuang
Ng, Wai Tung
INTEGRATION-THE VLSI JOURNAL, 2015, 51 : 107 - 117
[43] An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management
An, Young-Jae
Jung, Dong-Hoon
Ryu, Kyungho
Woo, Seung-Han
Jung, Seong-Ook
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (08) : 1508 - 1517
[44] A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture
Wang, Jinn-Shyan
Cheng, Chun-Yuan
Chou, Pei-Yuan
Yang, Tzu-Yi
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (11) : 2635 - 2644
[45] Compatibility and Interoperability Evaluation of All-digital Protection Systems Based on IEC 61850-9-2 Communication Standard
Djekic, Zarko
Portillo, Levi
Kezunovic, Mladen
2008 IEEE POWER & ENERGY SOCIETY GENERAL MEETING, VOLS 1-11, 2008, : 1661 - +
[46] A low-power preamble detection methodology for packet based RF modems on all-digital sensor front-ends
Gunnam, K.
Choi, G.
Yeary, M.
Zhai, Y.
2007 IEEE INSTRUMENTATION & MEASUREMENT TECHNOLOGY CONFERENCE, VOLS 1-5, 2007, : 1117 - +
[47] A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique
Lo, Yu-Lung
Fan, Fang-Yu
Wang, Hsi-Hua
Li, Yu-Hsin
Chen, Zi-Yi
Liu, Jen-Chieh
MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2021, 27 (04): : 1335 - 1346
[48] MEMS-based All-digital Frequency Synthesis for Ultralow-Power Radio for WBAN and WSN Applications (Invited Paper)
Ruffieux, David
Contaldo, Matteo
Enz, Christian
2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 157 - 160
[49] A Novel Hardware-Based All-Digital Phase-Locked Loop Applied to Grid-Connected Power Converters
Geng, Hua
Xu, Dewei
Wu, Bian
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2011, 58 (05) : 1737 - 1745
[50] A fast-lock low-power all-digital DLL-based clock generator with fractional multiple technique
Yu-Lung Lo
Fang-Yu Fan
Hsi-Hua Wang
Yu-Hsin Li
Zi-Yi Chen
Jen-Chieh Liu
Microsystem Technologies, 2021, 27 : 1335 - 1346

← 1 2 3 4 5 →